
IDT70V26S/L
High-Speed 16K x 16 Dual-Port Static RAM
Timing Waveform of Write with BUSY
t WP
R/ W "A"
t WB
Industrial and Commercial Temperature Ranges
BUSY "B"
t WH
(1)
R/ W "B"
(2)
2945 drw 13
,
NOTES:
1. t WH must be met for both BUSY input (SLAVE) and output (MASTER).
2. BUSY is asserted on port "B" blocking R/ W "B" , until BUSY "B" goes HIGH.
Waveform of BUSY Arbitration Controlled by CE Timing (1)
ADDR "A"
and "B"
CE "A"
CE "B"
t APS
(2)
ADDRESSES MATCH
t BAC
t BDC
BUSY "B"
2945 drw 14
Waveform of BUSY Arbitration Cycle Controlled by Address Match Timing (1)
ADDR "A"
ADDR "B"
t APS
(2)
ADDRESS "N"
MATCHING ADDRESS "N"
t BAA
t BDA
BUSY "B"
2945 drw 15
NOTES:
1. All timing is the same for left and right ports. Port “A” may be either the left or right port. Port “B” is the port opposite from port “A”.
2. If t APS is not satisfied, the BUSY signal will be asserted on one side or the other, but there is no guarantee on which side BUSY will be asserted.
12
6.42